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SC202A
Applications Information (continued)
calculating the minimum value required for C IN using the
following equation.
The following guidelines are recommended for designing
a PCB layout:
C IN
V OUT
V IN
V
I OUT
1
V OUT
V IN
ESR f
1. C IN should be placed as close to the IN and GND pins
as possible. This capacitor provides a low impedance
loop for the pulsed currents present at the buck
converter’s input. Use short wide traces to minimize
trace impedance. This will also minimize EMI and
The input voltage ripple is at maximum level when the
input voltage is twice the output voltage (50% duty cycle
scenario).
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capaci-
tor should be placed as close as possible to the IN and
GND pins. Table 3 lists recommended input capacitor
options from different manufacturers.
Table 3 — Recommended Input Capacitors
input voltage ripple by localizing the high frequency
current pulses.
2. C OUT should be connected as closely as possible to the
OUT pin.
3. Use a ground plane referenced to the GND pin. Use
several vias to connect to the component side ground
to further reduce noise and interference on sensitive
circuit nodes.
4. Route the output voltage feedback/sense trace
(connected to the SNS pin) away from the LX node
as shown in Figure 3 to minimize noise and magnetic
interference.
5. Minimize the resistance from the OUT and GND pins
Manufacturer
Part Nunber
Murata 
GRM188R60J475K
Murata 
GRM188R60J106K
Taiyo Yuden
JMK107BJ475KA
Value
(μF)
4.7±10%
10±10%
4.7±10%
Type
X5R
X5R
X5R
Rated
Voltage
(VDC)
6.3
6.3
6.3
Dimensions
LxWxH (mm)
Case Size
1.6x0.8x0.8
0603
1.6x0.8x0.8
0603
1.6x0.8x0.8
0603
to the load. This will reduce errors in DC regulation
due to voltage drops in the traces.
6. The two smaller exposed pads on this package should
not be connected to any traces. The area beneath
these two pads must be kept clear so that they do
not make electrical contact with any traces, including
ground.
CTL2
TDK
C1608X5R0J475KT
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
IN
These pads should not
be electrically
connected to the PCB.
CTL1
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended
PCB top-layer for the SC202A and supporting compo-
nents. Specified layout rules must be followed since the
layout is critical for achieving the performance specified in
the Electrical Characteristics table. Poor layout can
degrade the performance of the DC-DC converter and can
3.5mm
C IN
C OUT
GND
SC202A
LX
(no
connection
needed)
CTL0
CTL3
SNS
contribute to EMI problems, ground bounce, and resistive
voltage losses. Poor regulation and instability can also
result.
OUT
3.8mm
Figure 3 — Recommended PCB Layout
16
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